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1 ltc1143/ltc1143l LTC1143L-ADJ n dual outputs ltc1143, ltc1143l: 3.3v, 5v LTC1143L-ADJ: dual adjustable n very high efficiency: over 95% possible n current mode operation for excellent line and load transient response n high efficiency maintained over three decades of output current n low standby current at light loads: 160 m a/output n logic-controlled shutdown (ltc1143, ltc1143l) n wide v in range: 3.5v to 16v (ltc1143l, LTC1143L-ADJ) n very low dropout operation: 100% duty cycle n available in narrow 16-pin so package the ltc1143 series is a dual step-down switching regulator controller featuring automatic burst mode tm operation to maintain high efficiencies at low output currents. this device is composed of two separate regulator blocks, each driving an external power mosfet at switching frequencies up to 400khz using a constant off-time current mode architecture. both fixed and adjustable voltages are available. the operating current level for both regulators is user- programmable via an external current sense resistor. wide input supply range allows operation from 4v to 14v (16v maximum). the ltc1143l and LTC1143L-ADJ extend operation to v in = 3.5v. 100% duty cycle provides low dropout regulation limited only by the r ds(on) of the external mosfet and resistance of the inductor and current sense resistor. the ltc1143 series is ideal for applications requiring dual output voltages with high conversion efficiencies over a wide load current range in a small amount of board space. descriptio n u features figure 1. high efficiency dual 3.3v/2.5v regulator 1000pf 100pf + + + 1000pf p-drive 1 sense + 1 sense ? 1 v fb1 v fb2 gnd1 c t1 i th1 i th2 c t2 gnd2 sense ? 2 sense + 2 p-drive 2 v in1 v in2 LTC1143L-ADJ c t2 300pf 3 2 14 15 7 611 r c2 1k c c1 3300pf c c2 3300pf c t1 300pf r c1 1k 0.22 m f 13 5 12 9 8 10 4 1 16 v out2 2.5v/2a c out2 220 m f 10v 2 r sense2 0.05 w p1b l2 27 m h d2 mbrs320t3 0.22 m f c in2 22 m f 25v 2 c in1 22 m f 25v 2 p1a d1 mbrs320t3 c out1 220 m f 10v 2 l1 27 m h r sense1 0.05 w r2 82.5k 1% r1 49.9k 1% v out1 3.3v/2a r3 49.9k 1% r4 49.9k 1% v in 4v to 14v 1143 f01 + l1, l2: sumida cdrh125-270 p1: siliconix si4953dy/fairchild nds8947 r sense1, r sense2 : dale wsl-2010-.05 100pf burst mode is a trademark of linear technology corporation. , ltc and lt are registered trademarks of linear technology corporation. dual high efficiency so-16 step-down switching regulator controllers typical applicatio n u applicatio n s u n personal digital assistants n notebook and palmtop computers n battery-operated digital devices n portable instruments n dc power distribution systems
2 ltc1143/ltc1143l LTC1143L-ADJ absolute m axi m u m ratings w ww u input supply voltage (pins 5,13) ............... 16v to C0.3v continuous output current (pins 4,12) ................ 50ma sense voltages (pins 1, 8, 9, 16) v in 3 12.7v .......................................... 13v to C 0.3v v in < 12.7v .............................. (v in + 0.3v) to C 0.3v shutdown voltage (ltc1143, ltc1143l, pins 2, 10)...........7v to C 0.3v v fb current (LTC1143L-ADJ, pins 2, 10) ............... 1ma operating temperature range ambient .................................................. 0 c to 70 c extended commercial (note 4) ........... C40 c to 85 c junction temperature (note 1) ............................. 125 c storage temperature range .................. C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c package/order i n for m atio n w u u order part number ltc1143cs ltc1143lcs order part number ltc1143lcs-adj t jmax = 125 c, q ja = 95 c/w electrical characteristics t a = 25 c, v in = 10v unless otherwise noted. consult factory for industrial and military grade parts. symbol parameter conditions min typ max units v 2 , v 10 feedback voltage (LTC1143L-ADJ) v in = 9v l 1.21 1.25 1.29 v i 2 , i 10 feedback current (LTC1143L-ADJ) l 0.2 1 m a v out regulated output voltage (ltc1143/ltc1143l) v in3, v in5 = 9v, v 2 = v 10 = 0v 3.3v output i load = 700ma l 3.23 3.33 3.43 v 5v output i load = 700ma l 4.90 5.05 5.20 v d v out output voltage line regulation v in = 7v to 12v, i load = 50ma C40 0 40 mv output voltage load regulation v 2 = v 10 = 0v ltc1143/ltc1143l 3.3v output 5ma < i load < 2.0a l 40 65 mv 5v output 5ma < i load < 2.0a l 60 100 mv output ripple (burst mode) i load = 0a 50 mv p-p i 5 , i 13 input dc supply current (note 2) ltc1143: normal mode v 2 = v 10 = 0v, 4v < v in < 12v 1.6 2.1 ma sleep mode v 2 = v 10 = 0v, 4v < v in3 < 12v, 6v < v in5 < 12v 160 230 m a shutdown v 2 = v 10 = 2.1v, 4v < v in < 12v 10 20 m a ltc1143l: normal mode v 2 = v 10 = 0v, 3.5v < v in < 12v 1.6 2.1 ma sleep mode v 2 = v 10 = 0v, 3.5v < v in3 < 12v, 6v < v in5 < 12v 160 230 m a shutdown v 2 = v 10 = 2.1v, 3.5v < v in < 12v 10 20 m a LTC1143L-ADJ: normal mode 3.5v < v in < 12v 1.6 2.1 ma sleep mode 3.5v < v in < 12v, v out 3.3v 160 230 m a top view s package 16-lead plastic so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sense + 1 v fb1 gnd1 p-drive 1 v in2 c t2 i th2 sense 2 sense 1 i th1 c t1 v in1 p-drive 2 gnd2 v fb2 sense + 2 t jmax = 125 c, q ja = 95 c/w top view s package 16-lead plastic so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sense + 3 shutdown 3 gnd3 p-drive 3 v in5 c t5 i th5 sense 5 sense 3 i th3 c t3 v in3 p-drive 5 gnd5 shutdown 5 sense + 5
3 ltc1143/ltc1143l LTC1143L-ADJ electrical characteristics t a = 25 c, v in = 10v unless otherwise noted. symbol parameter conditions min typ max units v 1 to v 16 , current sense threshold voltage v 8 to v 9 ltc1143/ltc1143l v 2 = v 10 = 0v v sense C = v out + 100mv (forced) 25 mv v sense C = v out C 100mv (forced) l 130 150 170 mv LTC1143L-ADJ v sense C = 5v, v fb = v out /4 + 25mv (forced) 25 mv v sense C = 5v, v fb = v out /4 C 25mv (forced) l 130 150 170 mv v 2 , v 10 shutdown pin threshold 0.5 0.8 2 v ltc1143/ltc1143l i 2 , i 10 shutdown pin input current 0v < v shutdown = < 8v, v in3, v in5 = 16v 1.2 5 m a ltc1143/ltc1143l i 6 , i 14 c t pin discharge current v out in regulation, v sense- = v out 50 70 90 m a v out = 0v 2 10 m a t off off-time (note 3) c t = 390pf, i load = 700ma 4 5 6 m s t r , t f driver output transition times c l = 3000pf (pins 4, 12), v in = 6v 100 200 ns C40 c t a 85 c (note 4), v in = 10v unless otherwise noted. v 2 , v 10 feedback voltage (LTC1143L-ADJ) v in = 9v 1.20 1.25 1.30 v v out regulated output voltage v in3, v in5 = 9v ltc1143/ltc1143l 3.3v output i load = 700ma 3.17 3.33 3.43 v 5v output i load = 700ma 4.85 5.05 5.20 v i 5 , i 13 input dc supply current (note 2) ltc1143: normal mode v 2 = v 10 = 0v, 4v < v in < 12v 1.6 2.4 ma sleep mode v 2 = v 10 = 0v, 4v < v in3 < 12v, 6v < v in5 < 12v 160 260 m a shutdown v 2 = v 10 = 2.1v, 4v < v in < 12v 10 22 m a ltc1143l: normal mode v 2 = v 10 = 0v, 3.5v < v in < 12v 1.6 2.4 ma sleep mode v 2 = v 10 = 0v, 3.5v < v in3 < 12v, 6v < v in5 < 12v 160 260 m a shutdown v 2 = v 10 = 2.1v, 3.5v < v in < 12v 10 22 m a LTC1143L-ADJ: normal mode 3.5v < v in < 12v 1.6 2.4 ma sleep mode 3.5v < v in < 12v, v out 3.3v 160 260 m a v 1 to v 16 , current sense threshold voltage v 8 to v 9 ltc1143/ltc1143l v 2 = v 10 = 0v v sense C = v out + 100mv (forced) 25 mv v sense C = v out C 100mv (forced) 125 150 185 mv LTC1143L-ADJ v sense C = 5v, v fb = v out /4 + 25mv (forced) 25 mv v sense C = 5v, v fb = v out /4 C 25mv (forced) 125 150 185 mv v 2 , v 10 shutdown pin threshold 0.55 0.8 2 v ltc1143/ltc1143l the l denotes specifications which apply over the specified temperature range. note 1: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc1143 series: t j = t a + (p d ? 125 c/w) note 2: this supply current is for one regulator block. total supply current is the sum of pin 5 and pin 13 currents. dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 3: in applications where r sense is placed at ground potential, the off-time increases approximately 40%. note 4: the ltc1143 series is guaranteed to meet specified performance from 0 c to 70 c and is designed, characterized and expected to meet these extended temperature limits, but is not tested at C40 c to 85 c.
4 ltc1143/ltc1143l LTC1143L-ADJ typical perfor m a n ce characteristics uw load current (ma) efficiency (%) ltc1143 g02 1 70 90 95 100 10 100 1000 85 80 75 v in = 5v v in = 10v 5v output efficiency 3.3v output efficiency 5v efficiency vs input voltage 3.3v efficiency vs input voltage load regulation line regulation dc supply current supply current in shutdown operating frequency vs v in C v out input voltage (v) 0 efficiency (%) 100 98 96 94 92 90 88 86 84 82 80 4 8 1143 g03 12 16 i load = 100ma v out = 5v i load = 1a load current (ma) efficiency (%) ltc1143 g01 1 70 90 95 100 10 100 1000 85 80 75 v in = 6v v in = 10v input voltage (v) 0 efficiency (%) 100 98 96 94 92 90 88 86 84 82 80 16 ltc1143 g04 4 8 12 v out = 3.3v i load = 1a i load = 100ma input voltage (v) 0 d v out (mv) 40 30 20 10 0 10 20 30 ?0 16 ltc1143 g05 4 8 12 v out = 5v i load = 1a load current (a) 0 d v out (mv) 20 0 ?0 40 60 80 100 2.0 ltc1143 g06 0.5 1.0 1.5 2.5 r sense = 0.05 w v in = 6v v in = 6v v in = 12v v out = 5v v out = 3.3v v in = 12v input voltage (v) 0 0 supply current (ma) 0.3 0.9 1.2 1.5 4 ltc1143 ?g07 0.6 26 1.8 2.1 81012141618 not including gate charge current sleep mode active mode pins 5, 13 per regulator block input voltage (v) 0 supply current ( m a) 20 18 16 14 12 10 8 6 4 2 0 2 10 14 ltc1143 g08 8 18 4 6 12 16 per ltc1143/ltc1143l regulator block pins 5, 13 v shutdown = 2v (v in ?v out ) voltage (v) 0 normalized frequency 12 ltc1143 g09 2 68 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 4 10 v out = 5v 70? 0? 25?
5 ltc1143/ltc1143l LTC1143L-ADJ typical perfor m a n ce characteristics uw gate charge supply current operating frequency (khz) 20 gate charge current (ma) 140 14 12 10 8 6 4 2 0 ltc1143 g10 80 260 200 q p = 100nc q p = 29nc current sense threshold voltage temperature (?) 0 sense voltage (mv) 175 150 125 100 75 50 25 0 80 ltc1143 g12 20 40 60 100 maximum threshold minimum threshold output voltage (v) 0 off-time ( m s) 80 70 60 50 40 30 20 10 0 4 ltc1143 g11 1 2 3 5 v sense = v out v out = 5v v out = 3.3v off-time vs v out i th5 (pin 7): gain amplifier decoupling point, 5v section. the 5v section current comparator threshold increases with the pin 7 voltage. sense C 5 (pin 8): connects to internal resistive divider which sets the output voltage for the 5v section. pin 8 is also the (C) input for the current comparator on the 5v section. sense + 5 (pin 9): the (+) input to the 5v section current comparator. a built-in offset between pins 9 and 8 in conjunction with r sense 5 sets the current trip threshold for the 5v section. shutdown 5 (pin 10): when grounded, the 5v section operates normally. pulling pin 10 high holds the 5v section mosfet off and puts the 5v section in micropower shut- down mode. requires cmos logic level signal with t r , t f < 1 m s. do not float pin 10. gnd5 (pin 11): 5v section ground. two independent ground lines must be routed separately from other grounds to: 1) the (C) terminal of the 5v section output capacitor and 2) the cathode of the schottky diode d2 and (C) terminal of c in5 (see figure 9). p-drive 5 (pin 12): high current drive for top p-channel mosfet, 5v section. voltage swing at this pin is from v in5 to ground. pi n fu n ctio n s uuu ltc1143/ltc1143l sense + 3 (pin 1): the (+) input to the 3.3v section current comparator. a built-in offset between pins 1 and 16 in conjunction with r sense 3 sets the current trip threshold for the 3.3v section. shutdown 3 (pin 2): when grounded, the 3.3v section operates normally. pulling pin 2 high holds the mosfet off and puts the 3.3v section in micropower shutdown mode. requires cmos logic level signal with t r , t f < 1 m s. do not float pin 2. gnd3 (pin 3): 3.3v section ground. two independent ground lines must be routed separately from other grounds to: 1) the (C) terminal of the 3.3v section output capacitor and 2) the cathode of the schottky diode d1 and (C) terminal of c in3 (see figure 9). p-drive 3 (pin 4): high current drive for top p-channel mosfet, 3.3v section. voltage swing at this pin is from v in3 to ground. v in5 (pin 5): supply pin, 5v section. must be closely decoupled to 5v power ground pin 11. c t5 (pin 6): external capacitor c t5 from pin 6 to ground sets the operating frequency for the 5v section. (the actual frequency is also dependent upon the input voltage.)
6 ltc1143/ltc1143l LTC1143L-ADJ pi n fu n ctio n s uuu v in3 (pin 13): supply pin, 3.3v section. must be closely decoupled to 3.3v power ground pin 3. c t3 (pin 14): external capacitor c t3 from pin 14 to ground sets the operating frequency for the 3.3v section. (the actual frequency is also dependent upon the input voltage.) i th3 (pin 15): gain amplifier decoupling point, 3.3v section. the 3.3v section current comparator threshold increases with the pin 15 voltage. sense C 3 (pin 16): connects to internal resistive divider which sets the output voltage for the 3.3v section. pin 16 is also the (C) input for the current comparator on the 3.3v section. LTC1143L-ADJ sense + 1 (pin 1): the (+) input to the section 1 current comparator. a built-in offset between pins 1 and 16 in conjunction with r sense 1 sets the current trip threshold for section 1. v fb1 (pin 2): this pin serves as the feedback pin from an external resistive divider used to set the output voltage for section 1. gnd1 (pin 3): section 1 ground. two independent ground lines must be routed separately from other grounds to: 1) the (C) terminal of the section 1 output capacitor and 2) the cathode of the schottky diode d1 and (C) terminal of c in1 (see figure 1). p-drive 1 (pin 4): high current drive for top p-channel mosfet, section 1. voltage swing at this pin is from v in1 to ground. v in2 (pin 5): supply pin, section 2. must be closely decoupled to power ground pin 11. c t2 (pin 6): external capacitor c t2 from pin 6 to ground sets the operating frequency for section 2. (the actual frequency is also dependent upon the input voltage.) i th2 (pin 7): gain amplifier decoupling point, section 2. the section 2 current comparator threshold increases with the pin 7 voltage. sense C 2 (pin 8): pin 8 is the (C) input for the current comparator on section 2. sense + 2 (pin 9): the (+) input to the section 2 current comparator. a built-in offset between pins 9 and 8 in conjunction with r sense 2 sets the current trip threshold for section 2. v fb2 (pin 10): this pin serves as the feedback pin from an external resistive divider used to set the output voltage for section 2. gnd2 (pin 11): section 2 ground. two independent ground lines must be routed separately from other grounds to: 1) the (C) terminal of section 2 output capacitor and 2) the cathode of the schottky diode d2 and (C) terminal of c in2 (see figure 1). p-drive 2 (pin 12): high current drive for top p-channel mosfet, section 2. voltage swing at this pin is from v in2 to ground. v in1 (pin 13): supply pin, section 1. must be closely decoupled to power ground pin 3. c t1 (pin 14): external capacitor c t1 from pin 14 to ground sets the operating frequency for section 1. (the actual frequency is also dependent upon the input voltage.) i th1 (pin 15): gain amplifier decoupling point, section 1. the section 1 current comparator threshold increases with the pin 15 voltage. sense C 1 (pin 16): pin 16 is the (C) input for the current comparator on section 1.
7 ltc1143/ltc1143l LTC1143L-ADJ the ltc1143 series consists of two individual regulator blocks, each using current mode, constant off-time archi- tectures to switch an external power mosfet. the two ltc1143/ltc1143l regulators are internally set for 3.3v and 5v, while the two LTC1143L-ADJ regulators have externally programmable output voltages. operating fre- quency is individually set on each section by external capacitors at the timing capacitor pins 6 and 14. the output voltage is sensed by voltage comparator v and gain block g, which compare the divided output voltage with a reference voltage of 1.25v. to optimize efficiency, the ltc1143 series automatically switches between two modes of operation, burst and continuous. the voltage comparator is the primary control element when the device is in burst mode operation, while the gain block controls the output voltage in continuous mode. during the switch on cycle in continuous mode, current comparator c monitors the voltage between pins 1 (9) and 16 (8) connected across an external shunt in series with the inductor. when the voltage across the shunt reaches its threshold value, the p-drive output is switched to v in , turning off the p-channel mosfet. the timing capacitor connected to pin 14 (6) is now allowed to discharge at a rate determined by the off-time controller. the discharge current is made proportional to the feedback voltage to model the inductor current, which decays at a rate that is also proportional to the output voltage. when the voltage on the timing capacitor has discharged past v th1 , comparator t trips, setting the flip-flop. this causes the p-drive output to go low, turning the p-channel mosfet back on. the cycle then repeats. as the load current increases, the output voltage decreases slightly. this causes the output of the gain stage [pin 15 (7)] to increase the current comparator threshold, thus tracking the load current. the sequence of events for burst mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. when the output voltage is at or above the desired regulated value, the p-channel mosfet is held off by comparator v and the timing capacitor continues to discharge below v th1 . when the timing capacitor discharges past v th2 , voltage compara- tor s trips, causing the internal sleep line to go low. operatio n u refer to functional diagram and figure 1. + + reference 4(12) p-drive ground v in + v + c 25mv to 150mv + 1(9) v os 2(10) shutdown (ltc1143/ltc1143l) v fb (LTC1143L-ADJ) 100k x x 16(8) 1.25v 5pf g 15(7) i th q r s v in sense off-time control 14(6) 13k + s sleep v th1 c t t sense sense + v th2 1143 fd 13(5) 3(11) only one regulator block shown. connections shown for lt1143/ltc1143l; changes create LTC1143L-ADJ fu n ctio n al diagra uu w
8 ltc1143/ltc1143l LTC1143L-ADJ operatio n u refer to functional diagram and figure 1 the circuit now enters sleep mode with the power mosfet turned off. in sleep mode a majority of the circuitry is turned off, dropping the quiescent current from 1.6ma to 160 m a (for one regulator block). the load current is now being supplied from the output capacitor. when the output voltage has dropped by the amount of hysteresis in comparator v, the p-channel mosfet is again turned on and the process repeats. to avoid the operation of the current loop interfering with burst mode operation, a built-in offset (v os ) is incorpo- rated in the gain stage. this prevents the current compara- tor threshold from increasing until the output voltage has dropped below a minimum threshold. using constant off-time architecture the operating fre- quency is a function of the input voltage. to minimize the frequency variation as dropout is approached, the off-time controller increases the c t discharge current as v in drops below v out + 1.5v. in dropout the p-channel mosfet is turned on continuously (100% duty cycle), providing extremely low dropout operation. for figure 1 applications with v out below 2v, or when r sense is moved to ground, the current sense comparator inputs operate near ground. when the current comparator is operated at less than 2v common mode, the off-time increases approximately 40%, requiring the use of a smaller timing capacitor c t . r sense selection for output current r sense is chosen based on the required output current. the ltc1143 series current comparators have a threshold range that extends from a minimum of 25mv/r sense to a maximum of 150mv/r sense . the current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current i max equal to the peak value less half the peak-to-peak ripple current. for proper burst mode operation, i ripple(p-p) must be less than or equal to the minimum current comparator threshold. since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., i ripple(p-p) = 25mv/r sense . (see c t and l selection for operating frequency). solving for r sense and allowing a margin for variations in the ltc1143 series and external component values yields: r sense = 100mv i max a graph for selecting r sense versus maximum output current is given in figure 2. the basic LTC1143L-ADJ application circuit is shown in figure 1. the ltc1143 and ltc1143l are similar but omit the external resistive v out dividers (see figures 10 and 13). external component selection is driven by the load requirement and begins with v out and the selection of r sense . once r sense is known, c t and l can be chosen. next, the power mosfet and d1 are selected. finally, c in and c out are selected and the loop is compensated. since the two regulator sections are identical, the process of component selection is the same for both sections. the circuit shown in figure 1 can be configured for operation up to an input voltage of 16v. output voltage selection the ltc1143/ltc1143l output voltages are internally set to 3.3v and 5v. the LTC1143L-ADJ requires an external resistive divider from v out to v fb on each section as shown in figure 1. the regulated LTC1143L-ADJ output voltages are given by: v r r v r r out out 1 2 125 1 2 1 125 1 4 3 =+ ? ? ? ? =+ ? ? ? ? . . to prevent stray pickup, a 100pf capacitor is suggested across r1 and r3 located close to the LTC1143L-ADJ. applicatio n s i n for m atio n wu u u
9 ltc1143/ltc1143l LTC1143L-ADJ applicatio n s i n for m atio n wu u u maximum output current (a) 0 r sense ( w ) 0.20 0.15 0.10 0.05 0 4 1143 f02 1 2 3 5 figure 2. selecting r sense the load current below which burst mode operation commences, i burst , and the peak short circuit current, i sc(pk) , both track i max . once r sense has been chosen, i burst and i sc(pk) can be predicted from the following: i burst ? 15mv r sense i sc(pk) = 150mv r sense the ltc1143 series automatically extends t off during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. the resulting i sc(avg) to be reduced to approximately i max . l and c t selection for operating frequency each regulator section of the ltc1143 series uses a constant off-time architecture with t off determined by an external timing capacitor c t . each time the p-channel mosfet switch turns on the voltage on c t is reset to approximately 3.3v. during the off-time, c t is discharged by a current that is proportional to v out . the voltage on c t is analogous to the current in inductor l, which likewise decays at a rate proportional to v out . thus the inductor value must track the timing capacitor value. the value of c t is calculated from the desired continuous mode operating frequency: c f vv vv t in out in d = ? ? ? - + ? ? ? ? 1 13 10 4 . where v d is the drop across the diode. a graph for selecting c t versus frequency including the effects of input voltage is given in figure 3. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the complete expression for operating frequency of the circuit in figure 1 is given by: f t v v off out in ?- ? ? ? ? 1 1 where: tc v v off t reg out = ? ? ? ? ? ? ? 13 10 4 . v reg is the desired output voltage (i.e., 5v, 3.3v). v out is the measured output voltage. thus v reg /v out = 1 in regulation. note that as v in decreases, the frequency decreases. when the input-to-output voltage differential drops below 1.5v for a particular section, the ltc1143 series reduces t off in that section by increasing the discharge current in c t . this prevents audible operation prior to dropout. frequency (khz) 0 capacitance (pf) 50 100 150 200 ltc1143 f03 250 1000 800 600 400 200 0 300 v in = 12v v in = 10v v in = 7v v sense = v out = 5v figure 3. timing capacitor value
10 ltc1143/ltc1143l LTC1143L-ADJ once the frequency has been set by c t , the inductor l must be chosen to provide no more than 25mv/r sense of peak- to-peak inductor ripple current. this results in a minimum required inductor value of: l min = 5.1(10 5 )(r sense )(c t )v reg as the inductor value is increased from the minimum value, the esr requirements for the output capacitor are eased at the expense of efficiency. if too small an inductor is used, the inductor current will become discontinuous before the ltc1143 series enters burst mode operation. a consequence of this is that the ltc1143 series will delay entering burst mode operation and efficiency will be degraded at low currents. inductor core selection once the minimum value for l is known, the type of inductor must be selected. the highest efficiency will be obtained using ferrite, kool m m ? or molypermalloy (mpp) cores. lower cost powdered iron cores provide suitable performance, but cut efficiency by 3% to 7%. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple that can cause burst mode operation to be falsely triggered. do not allow the core to saturate! kool m m (from magnetics, inc.) is a very good, low loss core material for toroids with a soft saturation characteristic. molypermalloy is slightly more efficient at high ( > 200 khz) switching frequencies but quite a bit more expensive. toroids are very space efficient, especially when you can use several layers of wire, while inductors wound on bobbins are generally easier to surface mount. new designs for surface mount are available from coiltronics, coilcraft and sumida. applicatio n s i n for m atio n wu u u power mosfet selection an external power mosfet must be selected for use with each section of the ltc1143 series. the main selection criteria for the power mosfets are the threshold voltage v gs(th) , maximum v gs rating and on resistance r ds(on) . surface mount p-channel power mosfets are widely available in both single and dual configurations. logic level mosfets are specified for operation up to 20v maximum v gs and guarantee a maximum r ds(on) with v gs = 4.5v. newer sub logic level mosfets allow only 8v maximum v gs but guarantee r ds(on) with v gs = 2.7v. if v in will exceed 8v, logic level mosfets must be used; if conservatively specified, they are generally usable down to the 3.5v minimum v in rating of the ltc1143l and LTC1143L-ADJ. the maximum output current i max determines the r ds(on) requirement for the two mosfets. when the ltc1143 series is operating in continuous mode, the simplifying assumption can be made that either the mosfet or schottky diode is always conducting the average load current. the duty cycles for the mosfet and diode are given by: pch v schottky vv v in out d in - duty cycle v diode duty cycle = v out in ? -+ () from the duty cycles the required r ds(on) for each mosfet can be derived: pch p v i p out max p - r = v ds(on) in () ? ? ? ? + () 2 1 d where p p is the allowable power dissipation and d p is the temperature dependencies of r ds(on) . p p will be determined by efficiency and/or thermal requirements (see efficiency considerations). (1+ d p ) is generally given for a mosfet in the f orm of a normalized r ds(on) vs temperature curve, kool m m is a registered trademark of magnetics, inc.
11 ltc1143/ltc1143l LTC1143L-ADJ applicatio n s i n for m atio n wu u u rms current must be used. the maximum rms capacitor current is given by: ci vvv v in max out in out in required i rms ? - () [] 12 / this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. an additional 0.1 m f to 1 m f ceramic capacitor is also required on each v in line (pins 5, 13) for high frequency decoupling. the selection of c out is driven by the required (esr). the esr of c out must be less than twice the value of r sense for proper operation of the ltc1143 series: c out required esr < 2r sense optimum efficiency is obtained by making the esr equal to r sense . as the esr is increased up to 2r sense the efficiency degrades by less than 1%. if the esr is greater than 2r sense , the voltage ripple on the output capacitor will prematurely trigger burst mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. manufacturers such as nichicon and united chemicon should be considered for high performance capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr size/ratio of any aluminum electrolytic at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. in surface mount applications multiple capacitors may have to be parallel to meet the capacitance, esr or rms current handling requirements of the application. but d = 0.005/ c can be used as an approximation for low voltage mosfets. when selecting the p-channel power mosfet for each section, consideration should be given to using a dual mosfet with the other half used for the second regulator. assuming both sections are operating at similar currents, the required r ds(on) will be half the value of a single mosfet to stay within the package dissipation limit. remember that worst-case mosfet dissipation occurs at minimum v in . output diode selection (d1, d2) the schottky diodes d1 and d2 shown in figure 1 conduct during the off-time. it is important to adequately specify the diode peak current and average power dissipation to not exceed the diode ratings. the most stressful condition for the output diode is under short circuit (v out = 0v). under this condition the diode must safely handle i sc(pk) at close to 100% duty cycle. under normal load conditions the average current con- ducted by the diode is: i vv v v i diode in out d in load = -+ () () remember to keep lead lengths short and observe proper grounding (see board layout checklist) to avoid ringing and increased dissipation. the forward voltage drop allowable in the diode is calcu- lated from the maximum short-circuit current as: v p i f d sc pk ? () where p d is the allowable power dissipation and will be determined by efficiency and/or thermal requirements (see efficiency considerations). c in and c out selection in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low effective series resistance (esr) input capacitor sized for the maximum
12 ltc1143/ltc1143l LTC1143L-ADJ applicatio n s i n for m atio n wu u u during this recovery time v out can be monitored for overshoot or ringing which would indicate a stability problem. the pin 15(7) external components shown in the figure 1 circuit will prove adequate compensation for most applications. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 ? c load . thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. (for high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.) although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1143 series circuits: 1) dc bias current 2) mosfet gate charge current 3) i 2 r losses 4) voltage drop of the schottky diode. 1) the dc supply current is the current that flows into v in (pin 13 and pin 5) less the gate charge current. for v in = 10v the dc supply current for each section is 160 m a for no load and increases proportionally with load up to a constant 1.6ma after the ltc1143 series has entered continuous mode. because the dc bias current is aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. for example, if 200 m f/10v is called for in an application requiring 3mm height, (2) avx 100 m f/10v (p/n tpsd 107m010) could be used. consult the manufacturer for other specific recommendations. at low supply voltages a minimum capacitance at c out is needed to prevent an abnormal low frequency operating mode (see figure 4). when c out is made too small the output ripple at low frequencies will be large enough to trip the voltage comparator. this causes burst mode operation to be activated when the ltc1143 series would normally be in continuous operation. the output remains in regulation at all times. v in ?v out voltage (v) 0 c out ( m f) 1000 800 600 400 200 0 4 1143 f04 1 2 3 5 l = 50 m h r sense = 0.02 w l = 25 m h r sense = 0.02 w l = 50 m h r sense = 0.05 w figure 4. minimum value of c out checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load esr, where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out until the regulator loop adapts to the current change and returns v out to its steady-state value.
13 ltc1143/ltc1143l LTC1143L-ADJ shutdown considerations pins 2 and 10 on the ltc1143 and ltc1143l shut down their respective sections when pulled high. they require cmos logic level signals with t r , t f < 1 m s and must never be floated. the LTC1143L-ADJ gives up the pin-controlled shutdown function in order to gain feedback pins for programming the output voltages. output current (a) 0.01 efficiency (%) 90 95 1 ltc1143 ?f05 85 80 0.03 0.1 0.3 3 100 gate charge 1 2 ltc1143 i q i 2 r schottky diode figure 5. efficiency loss 8% as the load current increases from 0.5a to 2a. if schotky diode losses routinely exceed 5% consider using the synchronously switched ltc1142 series. figure 5 shows how the efficiency losses in one section of a typical ltc1143 series regulator end up being appor- tioned. the gate charge loss is responsible for the majority of the efficiency lost in the midcurrent region. if burst mode operation was not employed at low currents, the gate charge loss alone would cause efficiency to drop to unacceptable levels. with burst mode operation, the dc supply current represents the lone (and unavoidable) loss component, which continues to become a higher percent- age as output current is reduced. as expected, the i 2 r losses and schottky diode loss dominate at high load currents. other losses including c in and c out esr dissipative losses, mosfet switching losses and inductor core losses, generally account for less than 2% total additional loss. drawn from v in , the resulting loss increases with input voltage. for v in = 10v the dc bias losses are generally less than 1% for load currents over 30ma. however at very low load currents the dc bias current accounts for nearly all of the loss. 2) mosfet gate charge current results from switching the gate capacitance of the power mosfet. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc supply current. in continuous mode, i gatechg = ?(q p ). the typical gate charge for a 0.05 w p-channel power mosfet is 40nc. this results in i gatechg = 4ma in 100khz continuous opera- tion, for a 2% to 3% typical midcurrent loss with v in = 10v. note that the gate charge loss increases directly with both input voltage and operating frequency. this is the principal reason why the highest efficiency circuits operate at moderate frequencies. furthermore, it argues against using a larger mosfet than necessary to control i 2 r losses, since overkill can cost efficiency as well as money! 3) i 2 r losses are easily predicted from the dc resistances of the mosfet, inductor and current shunt. in continuous mode the average output current flows through l and r sense , but is chopped between the p-channel mosfet and schottky diode. the mosfet r ds(on) multi- plied by the p-channel duty cycle can be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if the r ds(on) = 0.1 w , r l = 0.15 w , and r sense = 0.05 w , then the total resistance is 0.3 w . this results in losses ranging from 3% to 10% as the output current increases from 0.5a to 2a. i 2 r losses cause the efficiency to roll off at high output currents. 4) the schottky diode is a major source of power loss at high currents and gets worse at high input voltages. the diode loss is calculated by multiplying the forward voltage drop times the schottky diode duty cycle multiplied by the load current. for example, assuming a duty cycle of 50% with a schottky diode forward voltage drop of 0.4v, the loss increases from 0.5% to applicatio n s i n for m atio n wu u u
14 ltc1143/ltc1143l LTC1143L-ADJ applicatio n s i n for m atio n wu u u the LTC1143L-ADJ outputs can be turned off in one of two ways: 1) by placing a power mosfet switch in the v in line to the entire regulator or 2) by pulling the v fb pin over 1.4v, which trips comparator v and forces p-drive high (see functional diagram). v fb can be pulled high with a small current, but any circuitry used to shut down the LTC1143L-ADJ in this manner must minimize v fb lead length to prevent noise coupling during normal operation. in the figure 6 circuit, taking shutdown high turns on pnp q sd that sources a current into v fb . to shut down properly, rsd must be chosen to pull v fb above 1.4v with v out at 0v and minimum v in . note that this technique depends on the load resistance to prevent v out from floating up due to the current flowing into v fb . 200k 100k shutdown r sd 100pf r1 50k r2 v fb v out v in 1143 f06 q sd figure 6. local v fb pull-up shuts down LTC1143L-ADJ design example as a design example, assume v in = 12v(nominal), v out = 3.3v, i max = 2a and ? = 200khz. r sense , c t and l can immediately be calculated: r sense = 100mv/2 = 0.05 w t off = (1/200khz)[1 C (3.3/12)] = 3.63 m s c t = 3.63 m s/(1.3 10 4 ) = 280pf (use 300pf) l min = 5.1(10 5 )(0.05 w) (300pf) 3.3v = 25 m h assume a dual p-channel power mosfet is to be used and dissipation is to be limited to 1w total at worst-case lowest v in = 4v. if t a = 50 c and the thermal resistance of the mosfet package is 50 c/w, then the junction temperature will be 100 c and d p = 0.005(100 C 25) = 0.38. the maximum r ds(on) for each mosfet can now be calculated: p - ch r ds(on) = () ()( ) ? ? = 1 2 41 332 138 011 2 .. .w allowing for v in being slightly below the v gs used to specify r ds(on) , this requirement can be met by half of a siliconix si4953dy, fairchild nds8947 or similar so-8 dual p-channel mosfet. the most stringent requirement for the schottky diode is with v out = 0v (i.e. short circuit). during a continuous short circuit, the worst-case schottky diode dissipation rises to: pi v v v d sc avg d out in = () - ? ? ? ? () 1 with the 0.05 w sense resistor, i sc(avg) = 2a will result, increasing the 0.4v schottky diode dissipation to 0.8w. c in will require an rms current rating of at least 1a at temperature and c out will require an esr of 0.05 w for optimum efficiency. troubleshooting hints since efficiency is critical to ltc1143 series applications it is very important to verify that the circuit is functioning correctly in both continuous and burst mode operation. the waveform to monitor is the voltage on the timing capacitor pins 6 and 14. in continuous mode (i load > i burst ) the voltage on the c t pin should be a sawtooth with a 0.9v p-p swing. this voltage should never dip below 2v as shown in figure 7a. when load currents are low (i load < i burst ) burst mode operation occurs. the voltage on the c t pin now falls to ground for periods of time as shown in figure 7b. if pin 6 or pin 14 is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. refer to the board layout checklist.
15 ltc1143/ltc1143l LTC1143L-ADJ applicatio n s i n for m atio n wu u u with the addition of r3 a current is generated though r1, causing an offset of: vv r rr offset out = + ? ? ? ? 1 13 if v offset > 25mv, the built-in offset will be cancelled and burst mode operation is prevented from occurring. since v offset is constant, the maximum load current is also decreased by the same offset. thus, to get back to the same i max , the value of the sense resistor must be lower: r mv i sense max ? 75 to prevent noise spikes from erroneously tripping the current comparator, a 1000pf capacitor is needed across pins 1 (16) and 9 (8). board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1143 series. these items are also illustrated graphi- cally in the layout diagram of figure 9. in general, each block should be self-contained with little cross coupling for best performance. check the following in your layout: 1) are the signal and power grounds segregated? the ltc1143 series gnd pin 3 (11) must return separately to: a) the power and b) the signal grounds. the power ground returns to the anode of the schottky diode and (C) plate of c in , which should have as short lead lengths as possible .the signal ground (b) con- nects to the (C) plate of c out . 2) does the ltc1143 series sense C pin 16 (8) connect to a point close to r sense and the (+) plate of c out ? 3) are the sense C and sense + leads routed together with minimum pc trace spacing? the 1000pf capacitor between pins 1 (9) and 16 (8) should be as close as possible to the ltc1143 series. 4) does the (+) plate of c in connect to the source of the p-channel mosfet as closely as possible? this capacitor provides the ac current to the p-channel mosfet. 3.3v 0v (a) continuous mode operation 3.3v 0v (b) burst mode operation ltc1143 ?f07 figure 7. c t waveforms auxiliary windingsCCsuppressing burst mode operation the ltc1143 series operates nonsynchronously with the normal limitation that the power drawn from the inductor primary winding must not be less than twice the power drawn from the auxiliary windings. (with synchronous switching, using the ltc1142 series, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation.) burst mode operation can be suppressed at low output currents with a simple external network that cancels the 25mv minimum current comparator threshold. this tech- nique is also useful for eliminating audible noise from certain types of inductors in high current (i out > 5a) applications when they are lightly loaded. an external offset is put in series with the sense C pin to subtract from the built-in 25mv offset. an example of this technique is shown in figure 8. two 100 w resistors are inserted in series with the sense leads from the sense resistor. r sense 1000pf r2 100 w r1 100 w r3 + c out v out sense + [pin 16 (8)] sense [pin 1(9)] 1143 f08 figure 8. suppression of burst mode operation
16 ltc1143/ltc1143l LTC1143L-ADJ applicatio n s i n for m atio n wu u u 5) is the v in decoupling capacitor (1 m f, 0.1 m f) con- nected closely between pin 13 (5) and gnd pin 3 (11)? this capacitor carries the mosfet driver peak currents. 6) for the ltc1143 and ltc1143l, are the shut- down pins 2 and 10 actively pulled to ground during normal operation? both shutdown pins are high impedance and must not be allowed to float. both pins can be driven by the same external signal if needed. 7) for the LTC1143L-ADJ, are the v fb pins 2 and 10 decoupled with 100pf as close to the device as possible? the v fb line is sensitive to noise pickup and should be kept away from the p-channel mosfet. figure 9. ltc1143 layout diagram (see board layout checklist) + + c out5 c in3 v out5 + r sense5 r sense3 l1 l2 p-ch d1 d2 1k *must be located close to ltc1143 shutdown (3.3v output) c t5 p-ch c in5 c out3 v in3 v in5 bold lines indicate high current paths shutdown (5v output) + v out3 + + 1000pf* 1000pf* 0.0033 f 1k c t3 0.0033 f + 0.22 f* 0.22 f* sense + 3 shutdown 3 p-drives3 c t5 i th5 sense 5 sense 3 i th3 c t3 p-drives5 shutdown 5 sense + 5 ltc1143 gnd5 v in5 v in5 v in3 v in3 gnd3 + 1143 f09
17 ltc1143/ltc1143l LTC1143L-ADJ + + + p-drive 3 sense + 3 sense ? 3 gnd3 gnd5 c t3 i th3 i th5 c t5 sense ? 5 sense + 5 p-drive 5 v in3 shutdown 5 v in5 ltc1143l c t5 220pf c t3 270pf 3141576 11 r c5 1k c c3 3300pf c c5 3300pf r c3 1k 13 10 5 12 9 8 4 1 16 v out5 5v/2a c out5 220 m f 10v 2 r sense5 0.05 w l2 25 m h d2 mbrs140t3 p1: fairchild nds8934 r sense3 : irc lr2512-01-or100g r sense5 : irc lr2512-01-oro5og d1 mbrs140t3 0v = normal >1.5v = shutdown c in5 22 m f 25v 2 c in3 22 m f 25v 2 p1a c out3 220 m f 10v l1 50 m h r sense3 0.10 w v out3 3.3v/1a v in range v out5 on: 5.2v to 8v v out5 shutdown: 3.5v to 8v + + p1b 0.01 m f 0.01 m f 1143 f10 0.22 m f 0.22 m f + shutdown 3 2 c in3 , c in5 : avx tpsd226k025r0200 c out3 , c out5 : avx tpse227m010r0080 l2: coiltronics ctx50-4 l2: coiltronics ctx25-4 1000pf 100pf + + + 1000pf 100pf p-drive 1 sense + 1 sense ? 1 v fb1 v fb2 gnd1 c t1 i th1 i th2 c t2 gnd2 sense ? 2 sense + 2 p-drive 2 v in1 v in2 LTC1143L-ADJ c t2 300pf 3 2 14 15 7 611 r c2 1k c c1 3300pf c c2 3300pf c t1 220pf r c1 510 0.22 m f 13 5 12 9 8 10 4 1 16 v out2 2.5v/2a c out2 220 m f 10v 2 r sense2 0.04 w 100 w 100 w p2 l2 27 m h d2 mbrs320t3 0.22 m f c in2 22 m f 25v 2 c in1 22 m f 25v 3 p1 d1 mbrs320t3 c out1 330 m f 6.3v 2 l1 15 m h r sense1 0.025 w 100 w 100 w r2 22.1k 1% 5.6k r1 49.9k 1% v out1 1.8v/3a r3 49.9k 1% r4 49.9k 1% 8.2k v in 4v to 14v 1143 f11 + c in1 , c in2 : avx tpsd226k025r0200 c out1 : avx tpse337m006r0100 c out2 : avx tpse227m010r0100 100pf p1: ir irf7406 p2: ir irf7204 l1: sumida cdrh125-150 l2: sumida cdrh125-270 r sense1 : dale wsl-2010-.025 r sense2 : dale wsl-2010-.04 figure 11. dual 1.8v/3a and 2.5v/2a with burst mode defeated figure 10. all surface mount low dropout dual 5v/2a, 3.3v/1a converter typical applicatio n s u
18 ltc1143/ltc1143l LTC1143L-ADJ figure 12. dual 3.3v/5v buck-boost regulator 1000pf 100pf + + + 1000pf 100pf p-drive 1 sense + 1 sense ? 1 v fb1 v fb2 gnd1 c t1 i th1 i th2 c t2 gnd2 sense ? 2 sense + 2 p-drive 2 v in1 v in2 LTC1143L-ADJ c t2 180pf 3 2 14 15 7 611 r c2 1k c c1 3300pf c c2 3300pf c t1 300pf r c1 1k 0.22 m f 13 5 12 9 8 10 4 1 16 v out2 5v/1a c out2 220 m f 10v 220 m f 10v r sense2 0.082 w p2 l2a l2b d2 mbrs130l 0.22 m f c in2 22 m f 25v 2 c in1 22 m f 25v 2 p1 d1 mbrs130l c out1 220 m f 10v 2 l1 27 m h r sense1 0.05 w r2 82.5k 1% r1 49.9k 1% v out1 3.3v/2a r3 49.9k 1% r4 150k 1% 1k mmbt2222alt1 overvoltage protection v in 3.5v to 10v 1143 f12 + c in1 , c in2 : avx tpsd226k025r0200 c out1 , c out2 : avx tpse227m010r0100 l1: sumida cdrh125-270 l2: pulse engineering pe-53718 z1 5.1v p1, p2: siliconix si9803dy r sense1 : irc 1206-r050f r sense2 : irc 1206-r082f z1: mmbz5231b typical applicatio n s u
19 ltc1143/ltc1143l LTC1143L-ADJ information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio n u dimensions in inches (millimeters) unless otherwise noted. 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 s16 0695 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610)
20 ltc1143/ltc1143l LTC1143L-ADJ ? linear technology corporation 1994 1143fa lt/tp 0598 rev a 2k ? printed in usa + + + + + + p-drive 3 sense + 3 sense ? 3 gnd3 gnd5 c t3 i th3 i th5 c t5 sense ? 5 sense + 5 p-drive 5 v in3 shutdown 3 shutdown 5 v in5 ltc1143 c t5 220pf c t3 200pf 3 14 15 7 6 11 r c5 1k r c3 510 c c3 3300pf c c5 3300pf 2 13 10 5 12 9 8 4 1 16 v out5 5v/2a c out5 220 m f 10v 2 r sense5 0.05 w l2 25 m h d2 mbrd340 c in3 , c in5 : avx tpsd226k025r0200 c out3 , c out5 : avx tpse227m010r0080 l1: coiltronics ctx10-4 l2: coiltronics ctx25-4 d1 mbrd340 0v = normal >1.5v = shutdown c in5 22 m f 25v 2 c in3 22 m f 25v 3 p1 c out3 220 m f 10v 3 l1 10 m h r sense3 0.033 w v out3 3.3v/3a v in 5.2v to 14v p2 0.01 m f 0.01 m f 0.22 m f 0.22 m f ltc1143.f13 p1: siliconix si4431dy p2: siliconix si9435dy r sense3 : krl sl-1/2-c1-0r033j r sense5 : krl sl-1/2-c1-0r050j figure 13. all surface mount dual 5v/2a, 3.3v/3a converter related parts part number description comments ltc1142 dual high efficiency synchronous step-down switching regulator synchronous equivalent to ltc1143, 4v < v in < 16v ltc1142l-adj dual high efficiency synchronous step-down switching regulator synchronous equivalent to LTC1143L-ADJ, 3.5v < v in < 16v ltc1142hv-adj dual high efficiency synchronous step-down switching regulator 4v < v in < 20v ltc1147l high efficiency step-down switching regulator controller (1/2) LTC1143L-ADJ in so-8 ltc1265 1.2a, high efficiency step-down dc/dc converter single channel with internal switch ltc1438 dual synchronous controller with power-on reset and constant frequency current mode, drives synchronous an extra comparator n-channel mosfets ltc1538-aux dual synchronous controller with auxiliary linear regulator up to four output voltages from g28 package controller and 5v standby ltc1539 dual synchronous controller with phase-locked loop full featured dual controller in g36 package and adaptive power tm operation adaptive power is a trademark of linear technology corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com typical applicatio n u

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